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EL1503A
Data Sheet March 26, 2007 FN7039.2
High Power Differential Line Driver
The EL1503A ADSL Line Driver contains two wideband high-voltage drivers which are ideally suited for both ADSL and HDSL2 applications. They can supply a 39.2VP-P signal into a 22 load while exhibiting very low distortion. The EL1503A also has a number of power saving features. The IADJ pin can be used to set the maximum supply current and the C0 and C1 pins can be used to digitally vary the supply current to one of four modes. These modes include full power, low power, terminate only and power down. The EL1503A uses current-feedback type amplifiers, which achieve a high slew rate while consuming moderate power. They retain their frequency response over a wide range of externally set gains. The EL1503A operates on 5V to 12V supplies and consumes only 12.5mA per amplifier. The device is supplied in a thermally-enhanced 20 Ld SOIC (0.300") and the small footprint (4x5mm) 24 Ld QFN packages. Center pins on each side of the 20 Ld and 16 Ld packages are used as ground connections and heat spreaders. The QFN package has the potential for a low JA (<40C/W) and dissipates heat by means of a thermal pad that is soldered onto the PCB. All package options are specified for operation over the full -40C to +85C temperature range.
Features
* High power ADSL driver * 39.2VP-P differential output drive into 22 * 42.4VP-P differential output drive into 65 * Driver 2nd/3rd harmonics of -66dBc/-72dBc at 2VP-P into 100 differential * Supply current of 12.5mA per amplifier * Supply current control * Power saving modes * Standard surface-mount packages * Ultra-small QFN package * Pb-free plus anneal available (RoHS compliant)
Applications
* ADSL line drivers * HDSL2 line drivers * Video distribution amplifiers
Pinouts
EL1503A (24 LD QFN) TOP VIEW
20 VOUTB 24 VOUTA 23 VIN-A 21 VIN-B
EL1503A [20 LD SOIC (0.300")] TOP VIEW
VIN-A 1 VOUTA 2 19 NC 18 NC 17 VS+ VS- 3 A GND* 4 GND* 5 GND* 6 GND* 7 VIN+A 8 C1 9 C0 10 POWER CONTROL LOGIC
+ +
20 VIN-B 19 VOUTB 18 VS+ B 17 GND* 16 GND* 15 GND* 14 GND* 13 VIN+B 12 IADJ 11 NC
NC 1 NC 2 VS- 3 NC 4 NC 5 NC 6 GND 7 C0 10 VIN+B 12 VIN+A 8 IADJ 11 C1 9 THERMAL PAD
22 NC
16 NC 15 NC 14 NC 13 GND
*GND pins are heat spreaders
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2003, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL1503A Ordering Information
PART NUMBER EL1503ACM EL1503ACM-T13 EL1503ACMZ (See Note) EL1503ACMZ-T13 (See Note) EL1503ACL EL1503ACL-T7 EL1503ACL-T13 EL1503ACLZ (See Note) EL1503ACLZ-T7 (See Note) EL1503ACLZ-T13 (See Note) PART MARKING EL1503ACM EL1503ACM EL1503ACMZ EL1503ACMZ 1503ACL 1503ACL 1503ACL 1503ACLZ 1503ACLZ 1503ACLZ TAPE & REEL 13" 13" 7" 13" 7" 13" PACKAGE 20 Ld SOIC (0.300") 20 Ld SOIC (0.300") 20 Ld SOIC (0.300") (Pb-Free) 20 Ld SOIC (0.300") (Pb-Free) 24 Ld QFN 24 Ld QFN 24 Ld QFN 24 Ld QFN (Pb-Free) 24 Ld QFN (Pb-Free) 24 Ld QFN (Pb-Free) PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN7039.2 March 26, 2007
EL1503A
s
Absolute Maximum Ratings (TA = +25C)
VS+ to VS- Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28V VS+ Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V VS- Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . -28V to 0.3V Input C0/C1 to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Driver VIN+ Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- to VS+ Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA Output Current from Driver (static) . . . . . . . . . . . . . . . . . . . . 100mA Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature Range . . . . . . . . . . . . . . . . . .-60C to +150C Operating Junction Temperature . . . . . . . . . . . . . . .-40C to +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER SUPPLY CHARACTERISTICS IS+(Full Power) IS-(Full Power) IS+(Low Power) IS-(Low Power) IS+(Terminate) IS-(Terminate) IS+(Power Down) IS-(Power Down) IGND
VS = 12V, RF = 1.5k, RL= 65, IADJ = C0 = C1 = 0V, TA = +25C. Amplifiers tested separately. DESCRIPTION CONDITIONS MIN TYP MAX UNIT
Positive Supply Current per Amplifier Negative Supply Current per Amplifier Positive Supply Current per Amplifier Negative Supply Current per Amplifier Positive Supply Current per Amplifier Negative Supply Current per Amplifier Positive Supply Current per Amplifier Negative Supply Current per Amplifier GND Supply Current per Amplifier
All outputs at 0V, C0 = C1 = 0V All outputs at 0V, C0 = C1 = 0V All outputs at 0V, C0 = 5V, C1 = 0V All outputs at 0V, C0 =5V, C1 = 0V All outputs at 0V, C0 = 0V, C1 = 5V All outputs at 0V, C0 = 0V, C1 = 5V All outputs at 0V, C0 = C1 = 5V All outputs at 0V, C0 = C1 = 5V All outputs at 0V
10 -15 7 -10.5 4 -6 0.75 -0.5
12.5 -11.5 9 -8 5.1 -4 1.05 -0.25 -1
16 -9 11.5 -6 7 -3 1.7 0.07
mA mA mA mA mA mA mA mA mA
INPUT CHARACTERISTICS VOS VOS IB+ IBIBROL eN iN VIH VIL IIH1 IIH0 IIL Input Offset Voltage VOS Mismatch Non-Inverting Input Bias Current Inverting Input Bias Current IB- Mismatch Transimpedance Input Noise Voltage -Input Noise Current Input High Voltage Input Low Voltage Input High Current for C1 Input High Current for C0 Input Low Current for C1or C0 C0 & C1 inputs C0 & C1 inputs C1 = 5V C0 = 5V C1 = 0V, C0 = 0V 1.5 0.75 -1 2.7 0.8 8 4 1 -30 -15 -15 -50 -30 0.4 0.8 3.5 13 30 15 15 50 30 mV mV A A A M nV/ Hz pA/ Hz V V A A A
OUTPUT CHARACTERISTICS VOUT Loaded Output Swing RL = 65 RL = 22 IOL IOUT Linear Output Current Output Current AV = 5, RL = 10, f = 100kHz, THD = --60dBc VOUT = 1V, RL = 1 10.3 9.3 10.6 9.8 450 1 V V mA A
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FN7039.2 March 26, 2007
EL1503A
Electrical Specifications
PARAMETER DYNAMIC PERFORMANCE BW HD2 -3dB Bandwidth 2nd Harmonic Distortion AV = +5 fC = 1MHz, RL = 100, VOUT = 2VP-P fC = 1MHz, RL = 25, VOUT = 2VP-P HD3 3rd Harmonic Distortion fC = 1MHz, RL = 100, VOUT = 2VP-P fC = 1MHz, RL = 25, VOUT = 2VP-P SR Slewrate VOUT from -8V to +8V Measured at 4V 700 80 -76 -72 -76 -72 1100 MHz dBc dBc dBc dBc V/s VS = 12V, RF = 1.5k, RL= 65, IADJ = C0 = C1 = 0V, TA = +25C. Amplifiers tested separately. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT
Typical Performance Curves
25 VS=12V AV=10 RL=100 25 RF=1.3k GAIN (dB) VS=5V AV=10 RL=100
RF=1.5k RF=1.82k
RF=1.3k
RF=1.5k RF=1.82k
GAIN (dB)
20 RF=2.0k RF=2.43k RF=2.74k 15 100K 1M 10M 100M
20 RF=2.0k RF=2.4k RF=2.74k 15 100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. DRIVER DIFFERENTIAL FREQUENCY RESPONSE vs RF (FULL POWER MODE)
FIGURE 2. DRIVER DIFFERENTIAL FREQUENCY RESPONSE vs RF (FULL POWER MODE)
25
VS=12V AV=10 RL=100
25 RF=1.5k RF=1.3k
VS=5V AV=10 RL=100
RF=1.3k RF=1.5k
RF=1.82k
GAIN (dB)
20 RF=2.0k RF=2.43k RF=2.74k 15 100K 1M 10M 100M
GAIN (dB)
RF=1.82k
20 RF=2.0k RF=2.4k RF=2.74k 15 100K 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. DRIVER DIFFERENTIAL FREQUENCY RESPONSE vs RF (2/3 POWER MODE)
FIGURE 4. DRIVER DIFFERENTIAL FREQUENCY RESPONSE vs RF (2/3 POWER MODE)
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FN7039.2 March 26, 2007
EL1503A Typical Performance Curves
25
(Continued)
VS=12V AV=10 RL=100 GAIN (dB) RF=1.82k RF=2.0k
25
VS=5V AV=10 RL=100
RF=1.84k RF=2.0k RF=2.43k RF=2.74k
GAIN (dB)
20 RF=2.43k RF=2.74k
20
15 100M
10M
1M
100K
15 100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. DRIVER DIFFERENTIAL FREQUENCY RESPONSE vs RF (TERMINATE MODE)
FIGURE 6. DRIVER DIFFERENTIAL FREQUENCY RESPONSE vs RF (TERMINATE MODE)
19
VS=12V AV=5 RL=100
19 RF=1.3k RF=1.5k RF=1.82k GAIN (dB)
VS=5V AV=5 RL=100
RF=1.5k RF=1.82k
GAIN (dB)
14 RF=2.0k RF=2.4k RF=2.74k
14 RF=2.0k RF=2.4k RF=2.74k
9 100K
1M
10M
100M
9 100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 7. DRIVER DIFFERENTIAL FREQUENCY RESPONSE vs RF (FULL POWER MODE)
FIGURE 8. DRIVER DIFFERENTIAL FREQUENCY RESPONSE vs RF (FULL POWER MODE)
19
VS=12V AV=5 RL=100
19 RF=1.3k RF=1.5k RF=1.82k GAIN (dB)
VS=5V AV=5 RL=100
RF=1.5k RF=1.82k RF=2.0k
GAIN (dB)
14 RF=2.0k RF=2.43k RF=2.74k
14 RF=2.4k RF=2.74k
9 100K
1M
10M
100M
9 100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. DRIVER DIFFERENTIAL FREQUENCY RESPONSE vs RF (2/3 POWER MODE)
FIGURE 10. DRIVER DIFFERENTIAL FREQUENCY RESPONSE vs RF (2/3 POWER MODE)
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FN7039.2 March 26, 2007
EL1503A Typical Performance Curves
19 RF=1.82k RF=2.0k RF=2.43k GAIN (dB) 14 RF=2.74k VS=12V AV=5 RL=100 1M 10M 100M GAIN (dB) 14 RF=2.4k RF=2.74k VS=5V AV=5 RL=100 1M 10M 100M FREQUENCY (Hz) RF=1.82k RF=2.0k
(Continued)
19
9 100K
9 100K
FREQUENCY (Hz)
FIGURE 11. DRIVER DIFFERENTIAL FREQUENCY RESPONSE vs RF (TERMINATE MODE)
100 100
FIGURE 12. DRIVER DIFFERENTIAL FREQUENCY RESPONSE vs RF (TERMINATE MODE)
25 20
POWER) IS+ (FULL R) IS- (FULL POWE
ER) IS+ (2/3 POW IS- (2/3 POWER)
IS+
eN (nV/Hz)
iN 10 10
iN (pA/Hz)
IS (mA)
15 10 5
eN
IS- (TERMINATE)
1 10 100 1K FREQUENCY (Hz) 10K
1 100K
0
0
2
4
6 VS (V)
8
10
12
FIGURE 13. DRIVER INPUT VOLTAGE and FEEDBACK CURRENT NOISE vs FREQUENCY
FIGURE 14. SUPPLY CURRENT vs SUPPLY VOLTAGE
0 SUPPLY REJECTION (dB) -20 -40 -60 -80 -100 10K LEFT DRIVER RIGHT DRIVER SUPPLY REJECTION (dB)
0 -20 -40 -60 -80 -100 10K RIGHT DRIVER
LEFT DRIVER
100K
1M 10M FREQUENCY (Hz)
100M
100K
1M 10M FREQUENCY (Hz)
100M
FIGURE 15. POSITIVE SUPPLY REJECTION vs FREQUENCY
FIGURE 16. NEGATIVE SUPPLY REJECTION vs FREQUENCY
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FN7039.2 March 26, 2007
EL1503A Typical Performance Curves
100 OUTPUT IMPEDANCE () VS=12V AV=1 RL=1.5k
(Continued)
100 TERMINATE 2/3 POWER OUTPUT IMPEDANCE ()
VS=5V AV=1 RL=1.5k
TERMINATE
10
10
2/3 POWER
1 FULL POWER
1
FULL POWER
0 10K
100K
1M FREQUENCY (Hz)
10M
100M
0 10K
100K
1M FREQUENCY (Hz)
10M
100M
FIGURE 17. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 18. OUTPUT IMPEDANCE vs FREQUENCY
-45
-55 HD (dB)
VS=12V AV=5 RL=100 fC=1MHz HD (dB)
-40
VS=5V -45 AV=5 R =100 -50 f L C=1MHz -55 -60 -65 -70 HD3 HD3
-65
-75
HD2
-75 -80 HD2 1 2 3 4 5 6 7 8
-85
1
5
9
13
17
21
-85
VOP-P (V)
VOP-P (V)
FIGURE 19. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE (FULL POWER)
FIGURE 20. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE (FULL POWER)
-50
VS=5V -55 AV=5 RL=100 f =1MHz -60 C HD (dB) HD (dB) -65 -70 -75 -80 -85 1 5 HD2 HD3
-40 VS=5V AV=5 RL=100 fC=1MHz
-50
-60 HD3 -70 HD2 -80
9
13
17
21
1
2
3
4
5
6
7
8
VOP-P (V)
VOP-P (V)
FIGURE 21. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE (2/3 POWER)
FIGURE 22. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE
7
FN7039.2 March 26, 2007
EL1503A Typical Performance Curves
-45 VS=12V -50 AV=5 RL=100 -55 fC=1MHz THD (dB) -60 -65 -70 FULL POWER -75 -80 1 5 9 13 17 21 -80 1 2 3 4 5 6 7 8 2/3 POWER THD (dB)
(Continued)
-40
VS=5V AV=5 RL=100 -50 fC=1MHz
-60
FULL POWER
-70
2/3 POWER
VOP-P (V)
VOP-P (V)
FIGURE 23. DIFFERENTIAL TOTAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE
FIGURE 24. DIFFERENTIAL TOTAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE
-60 -62 -64 -66 HD (dB) -68 -70 -72 -74 -76 -78 1 3 5 7 9 11 13 VOP-P (V) HD3 VS=12V AV=5 RL=100 fC=1MHz 15 17 19 HD (dB) HD2
-56 -60 HD2 -64 -68 -72 -76 -80 1 2 4 3 VOP-P (V) HD3 VS=5V AV=5 RL=100 fC=1MHz 5 6
FIGURE 25. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE (FULL POWER)
FIGURE 26. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE (FULL POWER)
-54 -56 -58 HD (dB) -60 -62 -64 -66 -68 -70 1
VS=12V AV=5 RL=100 fC=1MHz HD (dB) HD2
-58 -60 -62 -64 -66 -68 -70
VS=5V AV=5 RL=100 fC=1MHz
HD2
HD3
HD3
3
5
7
9
11
13
15
17
19
-72 1 2 3 4 VOP-P (V) 5 6
VOP-P (V)
FIGURE 27. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE (2/3 POWER)
FIGURE 28. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE (2/3 POWER)
8
FN7039.2 March 26, 2007
EL1503A Typical Performance Curves
-55
(Continued)
THD (dBc)
THD (dBc)
VS=12V A =5 -57 RV=100 L fC=1MHz -59 -61 -63 -65 -67 1 3 5 7
-55 -57 2/3 POWER -59 -61 -63 -65 -67 11 13 9 VOP-P (V) 15 17 19 1
VS=5V AV=5 RL=100 fC=1MHz 2/3 POWER
FULL POWER
FULL POWER
2
3
4 VOP-P (V)
5
6
7
FIGURE 29. DIFFERENTIAL TOTAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE
FIGURE 30. DIFFERENTIAL TOTAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE
35 30 25 20 15 10 AV=10 RF=1.82k 5 6 7 8
WE FULL PO R MO D E
3.5 3.0 PEAKING (dB) 2.5 2.0 1.5 1.0 0.5 12 0 5 6 7 8
2/3 POW
TERMIN
AV=10 RF=1.82k
A TE M OD E
BW (MHz)
2/3 POWER MODE
ER MO D
E
MODE TERMINATE
FULL POWER
MODE
9
10
11
9
10
11
12
VS (V)
VS (V)
FIGURE 31. DIFFERENTIAL BANDWIDTH vs SUPPLY VOLTAGE
FIGURE 32. DIFFERENTIAL PEAKING vs SUPPLY VOLTAGE
25 IS+ (FULL POWER) 20 IS- (FULL POWER) IS (mA) 15 10 5 0 IS+ 2/3 POWER) IS- 2/3 POWER)
25 VS = 12V RSET to GND 20 15 10 5 0 0 2 4 6 8 10 RSET (k) IS+ (FULL POWER) IS- (FULL POWER) IS (mA) IS+ 2/3 POWER)
VS = 5V RSET to GND
IS+ (TERMINATE) IS- (TERMINATE)
IS- 2/3 POWER) IS+ (TERMINATE) IS- (TERMINATE)
0
2
4
6
8
10
RSET (k)
FIGURE 33. IS vs RSET
FIGURE 34. IS vs RSET
9
FN7039.2 March 26, 2007
EL1503A Typical Performance Curves
25 20 15 10 5 0 VS = 12V
O LP
(Continued)
25 20 15 10 5 0
R) WE
L PO R) ( FU LL WE I S+ - (FU /3 PO R) (2 E IS I S+ OW /3 P - (2 IS ) AT E RMIN + (TE IS E) INAT E RM I - (T
S
R) WE
VS = 12V
R) WE PO ) LL ER (FU OW ) I S+ LL P ER U OW ) - (F (2/3 P ER IS I S+ OW /3 P - (2 IS E) INAT ERM I S+ (T ATE) IN E RM I S- (T
IS (mA)
0
100
200
300
400
500
IS (mA)
0
100
200
300
400
500
ISET (A)
ISET (A)
FIGURE 35. IS vs ISET
FIGURE 36. IS vs ISET
4.5 4.0 POWER DISSIPATION (W) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -20 0 20 40 60 80 100 JA = 43C/W JA = 53C/W JA = 80C/W JA = 30C/W POWER DISSIPATION (W) 3.0 2.5 2.0 1.5 1.0 0.5 0
POWER DISSIPATION & THERMAL RESISTANCE USING JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD, QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5
2.703W
24 W F N C / Q 7 =3 J
A
AMBIENT TEMPERATURE (C)
0
25
50
75 85 100
125
150
FIGURE 37. POWER DISSIPATION vs AMBIENT TEMPERATURE for VARIOUS MOUNTED JAs
AMBIENT TEMPERATURE (C)
FIGURE 38. POWER DISSIPATION vs AMBIENT TEMPERATURE
10
FN7039.2 March 26, 2007
EL1503A Test Circuit
1 VIN-A 2 VOUTA 3 VS4 GND 5 GND 6 GND 7 GND 8 VIN+A 9 C1 10 C0 VIN-B 20 VOUTB 19 VS+ 18 GND 17 GND 16 GND 15 GND 14 VIN+B 13 IADJ 12 NC 11
RS R3 56 1/2W R7 LEFT DRIVER OUT 1.5k 1 2
+
100 1W
R4 56 1/2W
332 20 19 A
-
R16 1.5k RIGHT DRIVER OUT VS+
3 0.1F TANTALUM GND C2 5F 4 5 6 7 LEFT DRIVER IN 8 R2 51 10 C1 C0 9
B
+
18 5F 17 16 15 14 13 12 11 RSET R17 51 C1 0.1F
TANTALUM GND
RIGHT DRIVER IN
11
FN7039.2 March 26, 2007
EL1503A Pin Descriptions
20 Ld SOIC (0.300") 1 24 Ld QFN 23 PIN NAME VIN-A FUNCTION Channel A Inverting Input CIRCUIT
CIRCUIT 1 2 3 4, 5, 6, 7 8 24 3 7 8 VOUTA VSGND VIN+A Channel A Output Negative Supply Ground Connection Channel A Non-Inverting Input
VS+
(Reference Circuit 1)
CIRCUIT 2 9 9 C1 Current Control Bit 1
VS+
VS-
6.7V
CIRCUIT 3 10 11 10 1, 2, 4, 5, 6, 14, 15, 16, 18, 19, 22 11 C0 NC Current Control Bit 0 Not Connected (Reference Circuit 3)
12
IADJ
Supply Current Control Pin
VS+
CIRCUIT 4 13 14, 15, 16, 17 18 19 20 12 13 17 20 21 7 VIN+B GND VS+ VOUTB VIN-B Channel B Non-Inverting Input Ground Connection Positive Supply Channel B Output Channel B Inverting Input Reserve for Future Use (Reference Circuit 1) (Reference Circuit 1) Internally Unconnected (Reference Circuit 2)
12
FN7039.2 March 26, 2007
EL1503A Applications Information
The EL1503A consists of two high-power line driver amplifiers that can be connected for full duplex differential line transmission. The amplifiers are designed to be used with signals up to 4MHz and produce low distortion levels. A typical interface circuit is shown in Figure 39 below.
DRIVER INPUT
+ -
can cause ringing or even oscillations. This inductance is equivalent to about 4" of unshielded wiring, or 6" of unterminated transmission line. Normal high-frequency construction obviates any such problem.
Power Supplies & Dissipation
Due to the high power drive capability of the EL1503A, much attention needs to be paid to power dissipation. The power that needs to be dissipated in the EL1503A has two main contributors. The first is the quiescent current dissipation. The second is the dissipation of the output stage. The quiescent power in the EL1503A is not constant with varying outputs. In reality, 7mA of the 12.5mA needed to power each driver is converted in to output current. Therefore, in the equation below we should subtract the average output current, IO, or 7mA, whichever is the lowest. We'll call this term IX. Therefore, we can determine a quiescent current with the equation:
ROUT RF
LINE +
RG ZLINE RF
+
ROUT LINE RF R RIN
RECEIVE OUT +
+
RECEIVE AMPLIFIERS
RECEIVE OUT -
RF
+ -
R RIN
P Dquiescent = V S x ( I S - 2I X )
where: VS is the supply voltage (VS+ to VS-) IS is the maximum quiescent supply current (IS+ + IS-) IX is the lesser of IO or 7mA (generally IX = 7mA) The dissipation in the output stage has two main contributors. Firstly, we have the average voltage drop across the output transistor and secondly, the average output current. For minimal power dissipation, the user should select the supply voltage and the line transformer ratio accordingly. The supply voltage should be kept as low as possible, while the transformer ratio should be selected so that the peak voltage required from the EL1503A is close to the maximum available output swing. There is a trade of however with the selection of transformer ratio. As the ratio is increased, the receive signal available to the receivers is reduced. Once the user has selected the transformer ratio, the dissipation in the output stages can be selected with the following equation:
VS P Dtransistors = 2 x I O x ------ - V O 2
FIGURE 39. TYPICAL LINE INTERFACE CONNECTION
The amplifiers are wired with one in positive gain and the other in a negative gain configuration to generate a differential output for a single-ended input. They will exhibit very similar frequency responses for gains of three or greater and thus generate very small common-mode outputs over frequency, but for low gains the two drivers RF's need to be adjusted to give similar frequency responses. The positive-gain driver will generally exhibit more bandwidth and peaking than the negative-gain driver. If a differential signal is available to the drive amplifiers, they may be wired so:
+ -
RF RF
2RG
+
FIGURE 40. DRIVERS WIRED FOR DIFFERENTIAL INPUT
Each amplifier has identical positive gain connections, and optimum common-mode rejection occurs. Further, DC input errors are duplicated and create common-mode rather than differential line errors.
where: VS is the supply voltage (VS+ to VS-) VO is the average output voltage per channel IO is the average output current per channel The overall power dissipation (PDISS) is obtained by adding PDquiescent and PDtransistor.
Input Connections
The EL1503A amplifiers are somewhat sensitive to source impedance. In particular, they do not like being driven by inductive sources. More than 100nH of source impedance 13
FN7039.2 March 26, 2007
EL1503A
Then, the JA requirement needs to be calculated. This is done using the equation:
( T JUNCT - T AMB ) JA = -----------------------------------------------P DISS
where: TJUNCT is the maximum die temperature (150C) TAMB is the maximum ambient temperature PDISS is the dissipation calculated above
JA is the junction to ambient thermal resistance for the
technique, but several aspects of board layout should be noted. First, the heat should not be shunted to internal copper layers of the board nor backside foil, since the feedthroughs and fiberglass of the board are not very thermally conductive. To obtain the best thermal resistance of the mounted part, JA, the topside copper ground plane should have as much area as possible and be as thick as practical. If possible, the solder mask should be cut away from the EL1503A to improve thermal resistance. Finally, metal heatsinks can be placed against the board close to the part to draw heat toward the chassis.
package when mounted on the PCB
Output Loading
While the drive amplifiers can output in excess of 500mA transiently, the internal metallization is not designed to carry more than 100mA of steady DC current and there is no current-limit mechanism. This allows safely driving rms sinusoidal currents of 2 X 100mA, or 200mA. This current is more than that required to drive line impedances to large output levels, but output short circuits cannot be tolerated. The series output resistor will usually limit currents to safe values in the event of line shorts. Driving lines with no series resistor is a serious hazard. The amplifiers are sensitive to capacitive loading. More than 25pF will cause peaking of the frequency response. The same is true of badly terminated lines connected without a series matching resistor.
This JA value is then used to calculate the area of copper needed on the board to dissipate the power. The graph below show various JA for the SO20 mounted on different copper foil areas.
55 MOUNTED DEVICE JA (C/W) Note: 2oz. COPPER USED 50 TOP FOIL ONLY-WITH SOLDER MASK TOP FOIL-WITH 0.45IN2 BOTTOM FOIL WITH MANY FEEDTHROUGHS
45 40 35
TOP FOIL ONLY-NO SOLDER MASK
Power Supplies
30 0 1 2 3 4 5 6 7 8 9 10 AREA OF CIRCUIT BOARD HEAT SINK (in2)
FIGURE 41. THERMAL RESISTANCE of 20 Ld SOIC (0.300") EL1503A vs BOARD COPPER AREA
A separate application note details the 24 Ld QFN PCB design considerations.
Single Supply Operation
The EL1503A can also be powered from a single supply voltage. When operating in this mode, the GND pins can still be connected directly to GND. To calculate power dissipation, the equations in the previous section should be used, with VS equal to half the supply rail.
The power supplies should be well bypassed close to the EL1503A. A 3.3F tantalum capacitor for each supply works well. Since the load currents are differential, they should not travel through the board copper and set up ground loops that can return to amplifier inputs. Due to the class AB output stage design, these currents have heavy harmonic content. If the ground terminal of the positive and negative bypass capacitors are connected to each other directly and then returned to circuit ground, no such ground loops will occur. This scheme is employed in the layout of the EL1503A demonstration board, and documentation can be obtained from the factory.
Feedback Resistor Value
The bandwidth and peaking of the amplifiers varies with supply voltage somewhat and with gain settings. The feedback resistor values can be adjusted to produce an optimal frequency response. Here is a series of resistor values that produce an optimal driver frequency response (1dB peaking) for different supply voltages and gains:
TABLE 1. OPTIMUM DRIVER FEEDBACK RESISTOR for VARIOUS GAINS and SUPPLY VOLTAGES SUPPLY VOLTAGE 5V 12V DRIVER VOLTAGE GAIN 2.5 2.7k 2.2k 5 2.2k 2.0k 10 2.0k 2.0k
EL1503A PCB Design
A separate application note details the 24 Ld QFN PCB design considerations. The SOIC power packages (20 leads) are designed so that heat may be conducted away from the device in an efficient manner. To disperse this heat, the center leads (4 per side for the 20 lead and 2 per side for the 16 lead) are internally connected to the mounting platform of the die. Heat flows through the leads into the circuit board copper, then spreads and convects to air. Thus, the ground plane on the component side of the board becomes the heatsink. This has proven to be a very effective
14
FN7039.2 March 26, 2007
EL1503A
Power Control Function
The EL1503A contains two forms of power control operation. Two digital inputs, C0 and C1, can be used to control the supply current of the EL1503A drive amplifiers. As the supply current is reduced, the EL1503A will start to exhibit slightly higher levels of distortion and the frequency response will be limited. The 4 power modes of the EL1503A are set up as shown in the table 2.
TABLE 2. POWER MODES of the EL1503A C1 0 0 1 1 C0 0 1 0 1 OPERATION IS full power mode (CO or CP) 2/3 IS power mode (CO or CP) 1/3 IS terminate only mode Power down 12.5mA I S - = 0 + ( C 1 x 2 3 ) x -----------------------------------------( 1 + R SET / 1k ) 12.5mA + ( C 0 x 1 3 ) x -----------------------------------------( 1 + R SET / 1k )
Another method for controlling the power consumption of the EL1503A is to connect a resistor from the IADJ pin to ground. When this pin is grounded (the normal state), the supply current per channel is as per the specifications table on page 3. When a resistor is inserted, the supply current is scaled according to the "IS vs RSET" graphs on page 10 in the Performance Curves section. Both methods of power control can be used simultaneously. In this case, positive and negative supply currents (per amp) are given by the equations below:
12.5mA I S + = 1mA + ( C 1 x 2 3 ) x -----------------------------------------( 1 + R SET / 1k ) 12.5mA + ( C 0 x 1 3 ) x -----------------------------------------( 1 + R SET / 1k )
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN7039.2 March 26, 2007
EL1503A Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
16
FN7039.2 March 26, 2007
EL1503A QFN (Quad Flat No-Lead) Package Family
A D N (N-1) (N-2) B
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) MILLIMETERS SYMBOL QFN44 QFN3 A 0.90 0.02 0.25 0.20 7.00 5.10 7.00 5.10 0.50 0.55 44 11 11 0.90 0.02 0.25 0.20 5.00 3.80 7.00 5.80 0.50 0.40 38 7 12 QFN32 0.90 0.02 0.23 0.20 8.00 0.90 0.02 0.22 0.20 5.00 TOLERANCE 0.10 +0.03/-0.02 0.02 Reference Basic Reference Basic Reference Basic 0.05 Reference Reference Reference NOTES 8 8 4 6 5
1 2 3
A1
PIN #1 I.D. MARK E
b c D D2 E
(N/2)
5.80 3.60/2.48 8.00 6.00
2X 0.075 C
E2
2X 0.075 C
5.80 4.60/3.40 0.80 0.53 32 8 8 0.50 0.50 32 7 9
e L N ND
TOP VIEW N LEADS
0.10 M C A B (N-2) (N-1) N b
NE
L
PIN #1 I.D. 3 1 2 3
MILLIMETERS SYMBOL QFN28 QFN2 A A1 b c 0.90 0.02 0.25 0.20 4.00 2.65 5.00 3.65 0.50 0.40 28 6 8 0.90 0.02 0.25 0.20 4.00 2.80 5.00 3.80 0.50 0.40 24 5 7 QFN20 0.90 0.02 0.30 0.20 5.00 3.70 5.00 3.70 0.65 0.40 20 5 5 0.90 0.02 0.25 0.20 4.00 2.70 4.00 2.70 0.50 0.40 20 5 5 QFN16 0.90 0.02 0.33 0.20 4.00 2.40 4.00 2.40 0.65 0.60 16 4 4
TOLERANCE NOTES 0.10 +0.03/ -0.02 0.02 Reference Basic Reference Basic Reference Basic 0.05 Reference Reference Reference 4 6 5
(E2)
NE 5 (N/2)
D D2
(D2) BOTTOM VIEW
7
E E2 e L
e C SEATING PLANE 0.08 C N LEADS & EXPOSED PAD
0.10 C
N ND NE
Rev 11 2/07
SEE DETAIL "X" SIDE VIEW
NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device.
(c) C A
2
5. NE is the number of terminals on the "E" side of the package (or Y-direction). 6. ND is the number of terminals on the "D" side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet.
(L) A1 DETAIL X N LEADS
17
FN7039.2 March 26, 2007

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